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Purposes of pipelining

  • Utilize unused resources
    • Pipeline is intended to be "implementing instruction-level parallelism within a single processor" (Wikipedia: Instruction pipelining)
    • When a single process is executed, it only uses one part of the CPU. There is no reason not to use the other resources
    • Makes for a faster CPU without overclocking
  • Deeper stages of pipelining means that CPU can execute complex instructions with less complicated hardwares.

Instruction Cycle

  • Fetch–decode–execute cycle, repetitive operational process of a computer:
    • retrieves program instructions from memory.
    • dictates the instructions.
    • carries out those instructions.
  • In early CPUs, the instruction is executed sequentially.
  • In most modern general-purpose CPUs, instructions are executed in parallel through an instruction pipeline: next instructions starts before previous instruction has finished.

5 stages of Instruction Execution: IF – ID – EX – MEM – WB


image source

The instruction model below is MIPS architecture's model. Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following:

  1. Instruction Fetch (IF):
    • The program counter (PC) stores the memory location of current instruction, fetch the instruction of that memory address by sending read command to memory address register (MAR)
    • Save the returned data to instruction register for decoding.
    • Increment the PC by 4 so that it points to the next instruction.
  2. Instruction Decode/register fetch cycle (ID):
    • to determine what instruction to be performed so CPU can tell how may register values to fetch (two registers in MIPS)
    • compare two registers and set the EQUAL flag if equal
  3. Execution/effective address cycle (EX): to detect what instruction type to be performed:
    • Indirect memory reference: the effective address is read from memory and be added to register.
    • Direct memory operation / register-immediate ALU instruction: perform the instruction on the first register read and the immediate value in the instruction
    • Register-register ALU instruction: perform operations (e.g. addition, multiplication, logic operation) on two register values fetched from above ID stage.
  4. Memory access (MEM) : LOAD or STORE, otherwise do nothing. (In MIPS, update the PC using NPC or the output of ALU operation)
  5. Write-Back (WB) : if the instruction is LOAD, write the value from memory to register,; if it is an ALU operation, write the result to register.

Number of steps (stages)

  • Other processors have more than/less than 5 steps
  • Examples
    • Microcontrollers
      • PIC and AVR (arduino) each have 2 steps (most likely fetch and execution?)
    • Modern CPUs
      • 7, 10 and even 20 stages (as in the Intel Pentium 4).
      • "The Xelerated X10q Network Processor has a pipeline more than a thousand stages long"(Wikipedia: Instruction pipelining)

Pipeline hazards

Conflicts occur between different stages of the pipeline:

  • Structural hazard: when there is only a single resource, such as a single port to the main memory, and two instructions attempt to use that at the same time, one has to wait for another
  • Data hazard: an instruction try to use the result of the ALU operation but the operation hasn't completed. it must wait, sometimes more than 1 clock cycle
    • This can be solved by implementing "bubble"
  • Control hazard: when a brach occurs, one or more in-progress instructions must be aborted without changing the state of the system, and new instructions must be fetched

Synchronization barriers ?!


  1. Instruction Cycle
  2. Basics of Pipelining
  3. Step to execute instruction

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Last-modified: 2018-07-16 (月) 14:38:41 (368d)