[[Wiki Schedule]]

* Contents [#t3f629a4]


* ARM Instruction Set Architecture [#q80d4469]

** Overview [#k3267169]

|type|register register|
|endianness|little as default|
|branch evaluation|condition code, compare and brench|

- ARM is a RISC (Reduced Instruction Set Computer) architecture
-- 32 bit load-store architecture
--- The only memory instructions allowed are loads and stores
--- Three-operand forma: register – register/shifted register/immediate value – register
--- 32-bit wide integer: word (32 bits), halfword (16 bits), doubleword (64 bits)
-- Orthogonal register set
-- Most instructions execute in a single cycle 
- 2 main instruction sets:
-- 32-bit ARM instruction set
-- 16/32-bit Thumb instruction set
- Six basic modes + several more
-- User (unprivileged) 
-- FIQ - for high priority interrupt
-- IRQ - for low priority interrupt 
-- Supervisor - for software interrupt instruction
-- Abort - for memory access violations
-- Undef - for undefined instructions

** History [#dc5f478c]

- First developed by Acon Computers in the 1980s for its Personal Computers
- Originally stands for Acorn RISC Machine, later Advanced RISC Machine.
- Excel in cost, power consumption, and heat dissipation

** Application [#ba79e0de]

- Mobile device
- Desktop/server
- Embedded 

** Register set [#oc2b024c]


[[Image 1's source:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0210c/Cihhcjia.html]]

** ARM Instruction set [#y518fbe8]
[[Image 2's source:http://aelmahmoudy.users.sourceforge.net/electronix/arm/chapter2.htm]]

- 32 bits long
- Be conditionally executed: each instruction has condition field
- Load-store instruction set => no direct manipulation of memory contents
- Instructions:
-- Arithmetic operations: ADD, ADC, SUB, SBC, RSB, RSC
-- Comparisons: CMP, CMN, TST, TEQ
-- Logical operations: AND, EOR, ORR, ORN, BIC
-- Data movement between registers: MOV, MVN

-- Each perform a specific operation on one or two operands: register and barrel shifted register

*** Conditional execution [#k008a547]

- Postfix the instruction with condition code to execute conditionally without branches (predication)
- Reusing condition evaluation and updating condition can increase number of instruction while removing the need for many branches
- Predicate takes up to four of 32 bits in an instruction code
- S-bit condition code update executed if:
- S-bit condition code update if:
-- N: negative result
-- Z: zero result
-- C carry out duing arithmetic operation, shifter
-- V: overflow during arithmetic operation

*** Syntax example [#q1e6020d]

| SUB r0, r1, #5	| r0 = r1 - 5 |
| ADD r2, r3, r3, LSL #2 | r2 = r3 + (r3 * 4)|
| ANDS r4, r4, #0x20 | the condition code will be changed to reflect the instruction|
| ADDEQ r5, r5, r6 | if (EQ) r5 = r5 + r6 |
| LDR r0, [r1] | r0 = *r1 load into r0 from memory addressed by the content of r1 |

*** Instruction set extension via coprocessors [#t1d6d259]
- ARM instruction set can be extended with coprocessors
- Up to 16 coprocessors can be defined
- Each coprocessor can have up to 16 private registers of any size 

** Thumb Instruction set [#zf8083bc]

- 16-bit long instructions (some are 32-bit)
-- Optimized for code density from C code
-- Higher performance
-- Subset of the functionality of the ARM instruction set
-- Most Thumb instructions are executed unconditionally
-- Both ARM and Thumb instruction set can be used in a single executable file
--- Switch mode with BX, BLX instruction
--- Generally, switch at the function call

- Other instruction set available on ARMs
-- NEON in ARM v7
-- Vector floating point instruction

* Appendix [#p4438af1]
-- [[ARM Data Processing Instruction:https://developer.arm.com/products/architecture/a-profile/docs/100898/latest/data-processing-instructions]]

* Reference [#y5e13cb7]
1. https://www.youtube.com/watch?v=7LqPJGnBPMM 

2. http://www.ee.ic.ac.uk/pcheung/teaching/ee2_computing/lecture_9.pdf 

3. http://users.ece.utexas.edu/~valvano/EE345M/Arm_EE382N_4.pdf

4. http://vision.gel.ulaval.ca/~jflalonde/cours/1001/h17/docs/arm-instructionset.pdf

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