#author("2019-07-18T09:35:42+09:00","","")
#author("2019-07-18T09:37:39+09:00","","")
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*Memory DRAM, SRAM, SDRAM [#b70d733d]
**RAM(Random Access Memory) [#b97c63dd]
#ref(https://cdncontribute.geeksforgeeks.org/wp-content/uploads/ram.png,400x300)
Geeks for Geeks Deepanshi_Mittal

**SRAM(Static Random Access Memory) [#k286ee71]
-complicated circuit 
- high speed
- expensive
- cache
~Memory Cell
#ref(https://cdncontribute.geeksforgeeks.org/wp-content/uploads/SRAM.png,300x200)
~Geeks for Geeks SAYAN KUMAR PAL
~stores data by current flow using flip-flop circuit
~if power is supplied and current is always flowing, stored data can be kept.

- Read operation
~ the word line is activated by the address input
~ -> closes both the transistors T1 and T2
~ -> the bit values at points A and B are transmit to their bit lines
~ -> the sense/write circuit sent the output to the processor 
- Write Operation
~the address activates the word line to close both the switches
~ -> the bit value is provided
~ -> signals in bit lines are stored in the cell

**DRAM(Dynamic Random Access Memory)[#e0ab652e]
- simple circuit 
- high memory density 
- large power consumption
- main memory
~Memory Cell
#ref(https://cdncontribute.geeksforgeeks.org/wp-content/uploads/DRAM.png,300x200)
~Geeks for Geeks SAYAN KUMAR PAL
- required an operation to replenish the charge called "refresh"
~ one transistor(T) and one capacitor(C) in each cell
~ stores data by a capacitor, but charge gradually escapes as time passes

**SDRAM(Synchronous Dynamic Random Access Memory) [#z0d51327]
~DRAM operating in synchronization with clock signal
~ After late 1990~ prevailed as standard RAM 
~ enabled pipelining
~ latency: Delay from read command to data output
#ref(https://upload.wikimedia.org/wikipedia/commons/8/8b/SDR_SDRAM-1.jpg,300x100)
"Eight Hyundai SDRAM ICs on a PC100 DIMM package." Wikipedia Synchronous dynamic random-access memory
~typical clock speeds: 66Mhz, 100Mhz and 133MHz(15ns, 10ns, 7.5ns)
~typical clock speeds(bandwidth): 66Mhz, 100Mhz and 133MHz(15ns, 10ns, 7.5ns)
~Generally modularized in the form of 168-pin DIMMs(Dual Inline Memory Module), it can read and write 64 bits (no ECC) or 72 bits (ECC) at one time.

**Summary [#n193a447]
#ref(https://cdncontribute.geeksforgeeks.org/wp-content/uploads/difference-1.png,500x400)
Geeks for Geeks Deepanshi_Mittal

**References [#f710485e]
~Wikipedia Dynamic random-access memory. https://en.wikipedia.org/wiki/Dynamic_random-access_memory
~Wikipedia Static random-access memory. https://en.wikipedia.org/wiki/Static_random-access_memory
~Wikipedia Synchronous dynamic random-access memory. https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
~Geeks for Geeks Deepanshi_Mittal, Types of computer memory (RAM and ROM). https://www.geeksforgeeks.org/types-computer-memory-ram-rom/
~Geeks for Geeks SAYAN KUMAR PAL, Different Types of RAM (Random Access Memory). https://www.geeksforgeeks.org/different-types-ram-random-access-memory/

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