慶應義塾大学
2007年度 秋学期

コンピューター・アーキテクチャ
Computer Architecture

2007年度秋学期 月曜日3時限
科目コード: XXX / 2単位
カテゴリ:
開講場所:SFC
授業形態:講義
担当: Rodney Van Meter
E-mail: rdv@sfc.keio.ac.jp

第1回 10月15日 Lecture 2, October 15:
Processors: Basics of Instruction Sets

Outline of This Lecture

定量てきなデザイン概念
Review: Quantitative Principles of Design

Last time, we talked about Hennessy & Patterson's Five Principles:

  1. Take Advantage of Parallelism
  2. Principle of Locality
  3. Focus on the Common Case
  4. Amdahl's Law
  5. The Processor Performance Equation
I would add to this one imperative: Achieve Balance.

Take Advantage of Parallelism

Parallelism can be found by using multiple processors on different parts of the problem, or multiple functional units (floating point units, disk drives, etc.), or by pipelining, dividing an individual computer instruction into several parts and executing the parts of different instructions at the same time in different parts of the CPU.

Principle of Locality

Programs and data tend to reuse data and instructions that have been recently used. There are two forms of locality: spatial and temporal. Locality is what allows a cache memory to work.

Focus on the Common Case

The things that are done a lot should be fast; the things that are rare may be slow.

Amdahl's Law

Amdahl's Law tells us how much improvement is possible by making the common case fast, or by parallelizing part of the algorithm. In the example below, 3/5 of the algorithm can be parallelized, meaning that three times as much hardware applied to the problem gains us only a reduction from five time units to three.

Example of Amdahl's Law, parallel and
				serial portions.

Some problems, most famously graphics, are known as "embarrassingly parallel" problems, in which extracting parallelism is trivial, and performance is primarily determined by input/output bandwidth and the number of processing elements available. More generally, the parallelism achievable is determined by the dependency graph. Creating that graph and scheduling operations to maximize the parallelism and enforce correctness is generally the shared responsibility of the hardware architecture and the compiler.

Dependency graph for the
					     above figure.

プロセッサー・パフォマンス定式
The Processor Performance Equation

CPU time = (seconds )/ program = (Instructions )/ program × (Clock cycles )/ Instruction × (Seconds )/ Clock cycle


Instruction Sets

命令:基本の概念
Instructions: the Basic Idea

Computers execute instructions, which are usually compiled by a compiler, a piece of software that translates human-readable (usually ASCII) code into computer-readable binary.

コンピューターが命令を実行する。その命令はコンパイラーが人間の 読めるプログラムから通訳してある。例えば:

LOAD	R1, A
ADD	R1, R3
STORE	R1, A
This example shows three instructions, to be executed sequentially. The first instruction LOADs a value into register R1 from memory (we will come back to how the value that is loaded into R1 is found in a minute). The second instruction ADDs the contents of register R3 into register R1, then the third instruction STOREs the result into the original memory location.

CPU: the Central Processing Unit

ちょっと抽象的な絵ですが:

CPU block diagram
簡単に説明すると、CPUはこの機能の部品がある:

メモリー(記録):レジスター、スタック、ヒープ
Memory: Registers, Stacks, and Heaps

It is the job of the compiler to decide how to use the registers, stack, and heap most efficiently. Note that these functions apply to both user programs, or applications, and the operating system kernel.

命令の種類
Types of Instructions

Classes of Instructions Sets

The diagram below shows how data flows in the CPU, depending on the class of instruction set. (TOS = Top of Stack)

differences in data
						  flow for instruction
						  set classes

Memory Addressing

Each operand of an instruction must be fetched before the instruction can be executed. Data may come from (There are other addressing modes, as well, which we will not discuss.)

Immediate
ADD R4,#3
Regs[R4] ← Regs[R4] + 3
Register
ADD R4,R3
Regs[R4] ← Regs[R4] + Regs[R3]
Register Indirect
ADD R4, (R1)
Regs[R4] ← Regs[R4] + Mem[Regs[R1]]
Displacement
ADD R4, 100(R1)
Regs[R4] ← Regs[R4] + Mem[100+Regs[R1]]
Depending on the instruction, the data may be one of several sizes (using common modern terminology):

What an Instruction Looks Like

An instruction must contain the following:

Some architectures always use the same number of arguments, others use variable numbers. In some architectures, the addressing information and address are always the same length; in others they are variable.

In general, the arithmetic instructions are either two address or three address. Two-address operations modify one of the operands, e.g.

ADD R1, R3	; R1 = R1 + R3
whereas three-address operations specify a separate result register, e.g.
ADD R1, R2, R3	; R3 = R1 + R2
(n.b.: in some assembly languages, the target is specified first; in others, it is specified last.)

The MIPS architecture, developed in part by Professors Patterson and Hennessy, is relatively easy to understand. Its instructions are always 32 bits, of which 6 bits are the opcode (giving a maximum of 64 opcodes). rs and rt are the source and target registers, respectively. (Those fields are five bits; how many registers can the architecture support?) Instructions are one of three forms:

宿題
Homework

This week's homework (submit via email):

  1. Take your "hello, world" program from last time and compile to assembly code.
    1. What type of processor is your system?
    2. Find a copy of the Instruction Set Reference Manual for your processor (it should be available online somewhere).
    3. What class of instruction set is your processor, load-store, register-memory, or accumulator? (It's unlikely to be a pure stack machine.)
    4. Determine if your stack grows up or down. (You may need to use a debugger for this.)
    5. How many different opcodes are there for your processor? How long is the opcode field in an instruction?
    6. How many different addressing modes does your processor have?
  2. Read the text for next week.

Next Lecture

Next lecture:

第3回 10月22日
Lecture 3, October 22: Processors: Arithmetic

Readings for next time:

Additional Information

その他