コンピューター・アーキテクチャ
Computer Architecture

Outline of This Lecture

• Follow-up on Arithmetic
• Stages of Instruction Execution
• Pipelining
• Final Thoughts
• Homework

Follow-up on Arithmetic

• The K'NEX Computer
• The Subjectivity of Computers
• Accuracy in the Babbage Difference Engine

I also spent part of this past week myself chasing a floating point precision bug.

Stages of Instruction Execution

1. Instruction Fetch cycle (IF)
   Fetch the current instruction from memory, using the program counter (PC) as the address, add 4 to the PC, and store the PC (actually, in MIPS, store the tentative new PC into an internal register called NPC, Next PC).
2. Instruction Decode/register fetch cycle (ID)
   Determine which instruction we are holding, fetch the register values (two, always, in this instruction set), compare the two registers and set the EQUAL flag if equal.
3. Execution/effective address cycle (EX)
   Depending on the instruction type:
   
   • Memory reference: The ALU adds the base register and the offset to form the effective address.
   • Register-Register ALU instruction: perform the operation (e.g., addition, multiplication, logic operation) on the register values fetched by the ID stage.
   • Register-Immediate ALU instruction: perform the instruction on the first register read and the immediate value in the instruction.
4. Memory access (MEM)
   If the instruction is a LOAD or a STORE, do the appropriate thing, otherwise do nothing. (In MIPS, update the PC using either NPC or the output of the ALU operation.)
5. Write-Back cycle (WB)
   If the instruction was LOAD, write the value fetched from memory into the matching register; if it was an ALU operation, write the result to the register.

The MIPS Pipeline

Pipeline Hazards

• Structural hazard: when there is only a single resource, such as a single port to access main memory, and two instructions try to use it at the same time, a structural hazard is hit and one must wait on the other.
• Data hazard:Sometimes one instruction will attempt to use the result of an ALU operation (addition, etc.) before the operation is complete. It must wait, sometimes more than one clock cycle.
• Control hazard:In the simplest pipeline implementations, every time a branch occurs, one or more in-progress instructions must be aborted without changing the state of the system, and new instructions must be fetched.

Final Thoughts

宿題
Homework

1. Find and describe a real-world pipeline. Include:
   1. The number of stages
   2. Functionality of each stage
   3. Interlocking between stages
   4. Any hazards
   5. How balance in execution time is maintained
2. We noted right at the end of class that pipeline hazards equate to arrows flowing right to left on the figure above. Identify the arrows on the diagram above by type and indicate the maximum delay that the hazard can cause.
3. The three pipeline programs we "executed" during class today are linked to below. Calculate the following for each:
   1. The number of instructions that must be executed. Don't forget to account for the loop in program 3. (n.b.: the #-28 in the branch is decimal!)
   2. The number of clock cycles the entire program takes, accounting for data and control hazards.
   3. The average clock cycles per instruction (CPI) for the three programs.

Next Lecture

第5回 11月12日
Lecture 4, November 12: Memory: Caching and Memory Hierarchy

• Follow-up from this lecture: Appendix A.1 and A.2
• For next time: Appendix C.1, C.2 and C.3

Additional Information

• The pipeline stages
• The first pipeline program
• The second pipeline program (data hazard)
• The third pipeline program (control hazard)
• The Wikipedia page on pipelining is decent.
• Class top page
• Elsevier's web page for the textbook.
• My web page on system software.

その他

• Rodney Van Meterのホームページ
• 徳田・村井・楠本・中村・高汐・重近・湧川・バンミーター研究プロジェクト