慶應義塾大学
2009年度 秋学期

コンピューター・アーキテクチャ
Computer Architecture

2007年度秋学期 火曜日3時限
科目コード: 35010 / 2単位
カテゴリ:
開講場所:SFC
授業形態:講義
担当: Rodney Van Meter
E-mail: rdv@sfc.keio.ac.jp

第7回 12月1日
Lecture 7, December 1: Processors: Basics of Pipelining

*** should use H&P slides! they're actually pretty good. ***

Outline of This Lecture

Follow-up on Assembly Programming

How did you fare on the assembly programming?

Follow-up on Arithmetic

Two weeks ago I meant to point out the following:

Stages of Instruction Execution

This model of how an instruction is executed is tilted slightly toward the MIPS architecture, of which Hennessy and Patterson were two of the instigators. However, the actions in any CPU would be similar.

  1. Instruction Fetch cycle (IF)
    Fetch the current instruction from memory, using the program counter (PC) as the address, add 4 to the PC, and store the PC (actually, in MIPS, store the tentative new PC into an internal register called NPC, Next PC).
  2. Instruction Decode/register fetch cycle (ID)
    Determine which instruction we are holding, fetch the register values (two, always, in this instruction set), compare the two registers and set the EQUAL flag if equal.
  3. Execution/effective address cycle (EX)
    Depending on the instruction type:
  4. Memory access (MEM)
    If the instruction is a LOAD or a STORE, do the appropriate thing, otherwise do nothing. (In MIPS, update the PC using either NPC or the output of the ALU operation.)
  5. Write-Back cycle (WB)
    If the instruction was LOAD, write the value fetched from memory into the matching register; if it was an ALU operation, write the result to the register.

The MIPS Pipeline

The MIPS Pipeline (Fig. A.17 in the text)

Pipeline Hazards

Sometimes conflicts occur between the different stages of the pipeline. Such as condition is called a pipeline hazard. There are three types of hazards:

Hazards result in pipeline stalls or pipeline bubbles.

Final Thoughts

The five-stage pipeline we have discussed is far from the only way to divide the work in a pipeline. The Intel Prescott microprocessor (Feb. 2004) had a thirty stage pipeline! Filling that pipeline takes some serious time, so every branch is a problem. The most famous pipeline of all:

Ford Model T assembly line, 1913, via
			       Wikipedia

宿題
Homework

This week's homework (submit via SFS):

  1. Take your assembly-language matrix multiplication program and count the following:
    1. Floating-point additions
    2. Floating-point multiplications
    3. Integer additions/subtractions
    4. Branches
    5. The number of instructions between branch instructions
  2. Calculate the ideal throughput, assuming one instruction per clock cycle, ****this should go in an earlier lecture?****
  3. Find and describe a real-world pipeline. Include:
    1. The number of stages
    2. Functionality of each stage
    3. Interlocking between stages
    4. Any hazards
    5. How balance in execution time is maintained
  4. Pipeline hazards equate to arrows flowing right to left on the figure above. Identify the arrows on the diagram above by type and indicate the maximum delay that the hazard can cause.
  5. The three pipeline programs we "executed" during class today are linked to below. Calculate the following for each:
    1. The number of instructions that must be executed. Don't forget to account for the loop in program 3. (n.b.: the #-28 in the branch is decimal!)
    2. The number of clock cycles the entire program takes, accounting for data and control hazards.
    3. The average clock cycles per instruction (CPI) for the program.

Next Lecture

Next lectures:

第8回 12月8日 and 12月12日
Lecture 8, December 8: Memory: Caching and Memory Hierarchy
Lecture 9, December 12 (Saturday!): Memory: Virtual Memory

Readings for next time:

Additional Information

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