Block diagram of a single processing element (PE). Note the many read/write ports on the register file. This means that the pipeline exhibits no structural hazards.
The pipeline is 8 stages:
The chip, mounted on a board:
Additional topics:
Last year, Intel announced a demonstration 80-core, single-chip multiprocessor capable of 1 teraFLOPS (10^9 32-bit floating point operations per second).
Block diagram of a single processing element (PE). Note the many read/write ports on the register file. This means that the pipeline exhibits no structural hazards.
The pipeline is 8 stages:
The chip, mounted on a board:
Note that each PE has a 3KB instruction memory, and a 2KB data memory. Data can be transferred to the network only from registers, not from memory. Their existing demonstration doesn't include a larger memory, but plans are for 3D packaging, with the memory chip stacked directly on top of the processor chip.
Programming this puppy requires a lot of very careful work to schedule the operations, including transfers to other processors on the network. Obviously, it is a message passing, or distributed memory, multiprocessor in its current form. The network is a 2D mesh.
Certainly the most famous chip multiprocessor at the moment is the Cell, used in the Sony PS3.
Intel says their 80-core processor runs at 1TFLOPS when the clock speed is 3.13GHz. Determine:
Next week, we will have the first of two lectures on I/O systems.
Next lecture:
第11回 1月18日 金曜日！ 入出力
Lecture 11, January 18 (n.b.: Friday!): Basics of I/O and
Storage Systems and Designing for Networks