慶應義塾大学
2012年度 秋学期
コンピューター・アーキテクチャ
Computer Architecture
第4回 10月18日 Lecture 4, October 18:
並列のデモ／プロセッサー：命令の基本
Parallel Demonstrations / Processors: Basics of Instruction Sets
Today's Pictures
Yesterday I gave a presentation at Quantum Horizons in Taipei. The guy on the right is Gerard 't Hooft, Nobel laureate in physics. The guy on the far left is Ray Beausoleil, HP Fellow. Ray made and interesting comment:
The success of quantum technologies will depend on packaging.
Outline of This Lecture
- Parallel Demonstrations
- Review: Processor Performance Equation
- Instruction Sets
- The basic idea
- Basic parts of a CPU
- Memory types and uses
- Instruction set classes
- Types of instructions
- Memory addressing
- What an instruction looks like
- Homework
Parallel Demonstrations
- Single-processor sum
- Parallel operation
- Reduction without locking
- Reduction with lock
- Sub-dividing reduction with lock
for ( i = 0 ; i < n ; i++ ) {
result += array[i];
}
#pragma omp parallel for
for ( i = 0 ; i < n ; i++ ) {
array[i] *= 2;
}
#pragma omp parallel for reduction(+:result)
for ( i = 0 ; i < n ; i++ ) {
result += array[i];
}
Review: プロセッサー・パフォマンス定式
The Processor Performance Equation
| CPU time = |
(seconds
)/
program
|
= |
(Instructions
)/
program
|
× |
(Clock cycles
)/
Instruction
|
× |
(Seconds
)/
Clock cycle
|
Instruction Sets
- CPUs execute instructions (命令)
- The data for those instructions comes from memory
(stack or heap) or registers
- An instruction includes an opcode
- Instructions may be ALU, data movement,
or control flow instructions
命令：基本の概念
Instructions: the Basic Idea
Computers execute instructions, which are usually compiled by
a compiler, a piece of software that translates human-readable
(usually ASCII) code into computer-readable binary.
コンピューターが命令を実行する。その命令はコンパイラーが人間の
読めるプログラムから通訳してある。例えば：
LOAD R1, A
ADD R1, R3
STORE R1, A
This example shows three instructions, to be executed sequentially.
The first instruction LOADs a value into register R1
from memory (we will come back to how the value that is loaded into R1
is found in a minute). The second instruction ADDs the
contents of register R3 into register R1, then the third
instruction STOREs the result into the original memory
location.
CPU: the Central Processing Unit
ちょっと抽象的な絵ですが：
簡単に説明すると、CPUはこの機能の部品がある：
- Instruction fetcherは命令をメモリーから読む。 The
instruction fetcher reads instructions from memory.
- Instruction decoderはその命令どのことか、処理する部分。メモ
リーからデータを読まなければならいかどうかを決める。
The instruction decoder decides what type of instruction is
being executed, and fetches data from memory if necessary.
- Memory interfaceは命令のために、メモリーを読んだり書いたり
する。 The memory interface reads and writes data from memory for
the instructions.
- RegistersはCPUの中のメモリーです。The registers are the
on-chip memory.
- ALU, Arithmetic and Logic Unit,は数学と論理の命令を実行する。
The ALU is the Arithmetic and Logic Unit actually
executes, as the name says, arithmetic and logical instructions.
メモリー（記録）：レジスター、スタック、ヒープ
Memory: Registers, Stacks, and Heaps
- Registers: Special memory inside the CPU chip. There are
typically only a few registers in a CPU. They are fast, but
expensive.
- Main Memory: Random Access Memory (RAM) is the
largest amount of memory in your system; you may have 512 megabytes
or more in your laptop. RAM is typically used in several ways:
- Stack: Also called a push-down stack, this area
of memory is used to keep values used as local variables
by functions in the program.
- Heap: Memory allocated to hold global variables
for the program.
- Binary/text segment: The program itself.
It is the job of the compiler to decide how to use the registers,
stack, and heap most efficiently. Note that these functions apply to
both user programs, or applications, and
the operating system kernel.
命令の種類
Types of Instructions
- ALU
- Integer arithmetic
- Bitfield and logical operations
- Floating point arithmetic (often handled in separate part of
the computer known as an FPU, or floating point
unit)
- Data load/store, stack push/pop
- Control flow
- Unconditional branch
- Conditional branch
- Function call/return
Classes of Instructions Sets
- Stack architecture
- Accumulator architecture
- General-purpose register architecture
- Register-memory
- Load-store
The diagram below shows how data flows in the CPU, depending on the
class of instruction set. (TOS = Top of Stack)
Memory Addressing
Each operand of an instruction must be fetched before the instruction
can be executed. Data may come from
- Immediate or literal data (limited to less than a
full word)
- Registers
- Register indirect
- Register displacement
(There are other addressing modes, as well, which we will not
discuss.)
| Immediate |
ADD R4,#3 |
Regs[R4] ← Regs[R4] + 3 |
| Register |
ADD R4,R3 |
Regs[R4] ← Regs[R4] + Regs[R3] |
| Register Indirect |
ADD R4, (R1) |
Regs[R4] ← Regs[R4] + Mem[Regs[R1]] |
| Displacement |
ADD R4, 100(R1) |
Regs[R4] ← Regs[R4] + Mem[100+Regs[R1]] |
Depending on the instruction, the data may be one of several sizes
(using common modern terminology):
- A byte (8 bits, today)
- A half word (16 bits)
- A word (32 bits)
- A double word (64 bits)
What an Instruction Looks Like
An instruction must contain the following:
- An opcode, the operation code that identifies the instruction.
- Address type for zero or more arguments (sometimes,
implicit in the instruction).
- Addresses (or immediate data) for zero or more arguments.
Some architectures always use the same number of arguments, others use
variable numbers. In some architectures, the addressing information
and address are always the same length; in others they are
variable.
In general, the arithmetic instructions are either two address
or three address. Two-address operations modify one of the
operands, e.g.
ADD R1, R3 ; R1 = R1 + R3
whereas three-address operations specify a separate result register,
e.g.
ADD R1, R2, R3 ; R3 = R1 + R2
(n.b.: in some assembly languages, the target is specified first; in
others, it is specified last.)
The MIPS architecture, developed in part by Professors Patterson and
Hennessy, is relatively easy to understand. Its instructions are
always 32 bits, of which 6 bits are the opcode (giving a
maximum of 64 opcodes). rs and rt are
the source and target registers, respectively. (Those fields are five
bits; how many registers can the architecture support?) Instructions
are one of three forms:
宿題
Homework
This week's homework (submit via SMS):
Programming:
- Install the MIPS simulator software on your laptop. You can get it from SourceForge.
Analysis:
- The problem set is here.
Next Lecture
Next lecture:
第5回 10月28日
Lecture 3, October 28: Processors: Instruction Sets and the Data Path
Readings for next time:
- Follow-up from this lecture:
- P-H: Ch. 2
- H-P: Appendix B.1 - B.7
- For next time:
Additional Information
その他