慶應義塾大学
2013年度 秋学期

コンピューター・アーキテクチャ
Computer Architecture

2013年度秋学期 火曜日3時限
科目コード: 35010 / 2単位
カテゴリ:
開講場所:SFC
授業形態:講義
担当: Rodney Van Meter
E-mail: rdv@sfc.keio.ac.jp

第5回 10月22日
Lecture 5, October 22: Instruction Sets and the Data Path, Simulation

Outline of This Lecture


Instruction Sets

命令:基本の概念
Instructions: the Basic Idea

Computers execute instructions, which are usually compiled by a compiler, a piece of software that translates human-readable (usually ASCII) code into computer-readable binary.

コンピューターが命令を実行する。その命令はコンパイラーが人間の 読めるプログラムから通訳してある。例えば:

LOAD	R1, A
ADD	R1, R3
STORE	R1, A
This example shows three instructions, to be executed sequentially. The first instruction LOADs a value into register R1 from memory (we will come back to how the value that is loaded into R1 is found in a minute). The second instruction ADDs the contents of register R3 into register R1, then the third instruction STOREs the result into the original memory location.

CPU: the Central Processing Unit

ちょっと抽象的な絵ですが:

CPU block diagram
簡単に説明すると、CPUはこの機能の部品がある:

メモリー(記録):レジスター、スタック、ヒープ
Memory: Registers, Stacks, and Heaps

It is the job of the compiler to decide how to use the registers, stack, and heap most efficiently. Note that these functions apply to both user programs, or applications, and the operating system kernel.

命令の種類
Types of Instructions

Classes of Instructions Sets

The diagram below shows how data flows in the CPU, depending on the class of instruction set. (TOS = Top of Stack)

differences in data
						  flow for instruction
						  set classes

Memory Addressing

Each operand of an instruction must be fetched before the instruction can be executed. Data may come from (There are other addressing modes, as well, which we will not discuss.)

Immediate
ADD R4,#3
Regs[R4] ← Regs[R4] + 3
Register
ADD R4,R3
Regs[R4] ← Regs[R4] + Regs[R3]
Register Indirect
ADD R4, (R1)
Regs[R4] ← Regs[R4] + Mem[Regs[R1]]
Displacement
ADD R4, 100(R1)
Regs[R4] ← Regs[R4] + Mem[100+Regs[R1]]
Depending on the instruction, the data may be one of several sizes (using common modern terminology):

What an Instruction Looks Like

An instruction must contain the following:

Some architectures always use the same number of arguments, others use variable numbers. In some architectures, the addressing information and address are always the same length; in others they are variable.

In general, the arithmetic instructions are either two address or three address. Two-address operations modify one of the operands, e.g.

ADD R1, R3	; R1 = R1 + R3
whereas three-address operations specify a separate result register, e.g.
ADD R1, R2, R3	; R3 = R1 + R2
(n.b.: in some assembly languages, the target is specified first; in others, it is specified last.)

The MIPS architecture, developed in part by Professors Patterson and Hennessy, is relatively easy to understand. Its instructions are always 32 bits, of which 6 bits are the opcode (giving a maximum of 64 opcodes). rs and rt are the source and target registers, respectively. (Those fields are five bits; how many registers can the architecture support?) Instructions are one of three forms:

Using the MIPS Simulator

Note: The MIPS simulator is available on SourceForge. The original spim page is still on the web.

You will need vecadd.s, a short MIPS assembly program.

Here are screen shots from spim (Linux), xspim (Linux), PCspim (Windows) and spim and QtSpim (Mac) versions of the tool.

spim execution screenshot (Linux) spim register screenshot (Linux) spim register screenshot in hex (Linux)
xspim screenshot (Linux)
PCspim screenshot (Windows) PCspim screenshot, with
  output console (Windows)
spim screenshot (Mac)
QtSpim screenshot (Mac)

Things to note in the images above, as well as your own execution runs:

宿題
Homework

This week's homework:

  1. Write a program in C or C++ to multiply these two matrices
    Matrices to be multiplied (same as in exercise below)

Next Lecture

Next week, we will continue with the discussion of processor architecture, getting into the fun stuff: pipelining!

Next lecture:

第6回 10月29日 プロセッサー:パイプラインの基本
Lecture 6, October 29: Processors: Basics of Pipelining

Readings for next time:

Additional Information

その他